Dulari total harmonic distortion. h an input signal

Dulari
Tandon, International Institute of Information Technology, Naya Raipur, Email:[email protected]

Isha,
International Institute of Information Technology, Naya Raipur,Email:[email protected]

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Abstract: The concept of this paper is a dynamic
amplifier topology for analog-to-digital -converters. In this method an input
signal of 100 mVpp,  diff and 4× gain is
provided  to achieve  100-dB total harmonic distortion. h an input signal of 100 m Vpp ,  diff and 4× gain, it achieves ?100-dB total
harmonic distortion, the lowest ever reported for a dynamic amplifier.  This method has an improved linearity of 25
dB having twice the output swing. The improvement in linearity is accomplished
with a new linearization technique based on capacitive degeneration, which
exploits the exponential voltage-to-current relationship of MOSFET in weak
inversion. The proposed  amplifier in
this paper is fabricated in a 28-nm CMOS process.

Keywords: Amplifier, analog
linearization technique, analog-to-digital converter (ADC), capacitive
degeneration, digital nonlinearity calibration, integrator.

I.                   
INTRODUCTION

The demand for
analog-to-digital converters (ADC) having more bandwidth and lower power
consumption has been increased with the advancement of software defined radio
(SDR) technology. The demand for Software Defined Radio (SDR) technique  is increased because of its flexibility, cost
efficient having lot of advantages. But
in other  wireless communication systems
such as GSM or LTE, a weak signal is required  to be processed using blocker. So the wideband
analog-to-digital converter (ADC) is not sufficient for this system, because
the channel selection is done in the digital domain, not in the analog
front-end. Due to these blockers strict linearity is required(>80 dB) on the
analog-to-digital converters (ADC) 2, so the analog-to-digital converters (ADC)
nonlinearity cannot be improved just by digital filtering and it needs to be
power efficient 3.

Pipelined  analog-to-digital converts (ADCs) are chosen
for wide-bandwidth and moderate-to-high resolution (>10 b) applications. In
a pipelined analog-to-digital converters  (ADC), amplifiers are used to improve the
noise performance. For this they must have sufficiently low noise and
nonlinearity to enhance analog-to-digital converters’ performance. Since noise
is basic factor which exists in practical, to get  the desired noise level it requires a certain
amount of power consumption. Nonlinearity causes deterministic errors and it can
be improved by analog 4 or digital 5 techniques. The main objective  is to improve linearity with minimum possible
power consumption.

Residue amplification
with high linearity (>60 dB) traditionally depends upon closed-loop
amplifiers with high loop gain. However, these require large bandwidth,
reducing the power efficiency. Alternative amplifier techniques has been
introduced to improve the amplification efficiency. Dynamic amplifiers (or
integrators)  allow for the lowest
possible small-signal bandwidth and hence the lowest power consumption. However,
they demonstrate more nonlinearity. Digital nonlinearity standardisation can be
used for the error detection and correction. Although error detection and
correction can be done at a lower rate compared to the sampling speed (FS),
digital error correction needs logic operating at FS, and also consumes relative
power.

In this paper, a new
linearization technique is proposed that presents capacitive degeneration to
considerably improve the linearity of a integrator (dynamic amplifier). It
employs a cross-coupled capacitor configuration reduces capacitor size and
improves common-mode (CM) rejection capability. For compensation, the
amplifier can be placed in a slow control loop which digitally detects any
residual nonlinearity and minimizes it through an analog control-voltage with consuming
negligible power.

 

II.                 
CAPACITIVELY
DEGENERATED LINEARIZATION TECHNIQUE

The introduced linearization technique
assuming that the MOSFETs are biased in the weak inversion saturation region,
where their voltage-to-current (V–I) relationship is exponential. The same
concept can therefore be applied to bipolar junction transistors as well, since
their V –I characteristic is also exponential. In this section, the CDL
technique is first explained intuitively, and then analytically. Finally, the
effect of this technique on the amplifier’s overall noise performance is
discussed.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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